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A novel space vector modulation (SVM) technique for a three-level five-phase inverter is described based on an optimized five vectors concept. The concept utilizes a novel vector minimization technique that reduces the number of vectors in the d1-q1 vector space by identifying candidate vectors in each of the ten sectors that comprise the decagon vector space. The candidate vectors are selected based on the inequality relationship between the five-phase voltages during each switching cycle. Using this technique, the original 243 inverter states are reduced to 113 candidate vectors, and from the remaining states ten possible switching sequences in each sector are utilized to develop the desired voltage reference in the d1-q1 vector space while forcing a null vector in the d3-q3 vector space. A novel region determination technique is also introduced to identify the subregion that the d1-q1 voltage vector occupies. This technique significantly reduces the computational overhead required when implementing SVM techniques with multilevel and multiphase inverters. The space vector technique can utilize redundant vectors to assist in balancing subcycle variation of the dc-link capacitor voltage under unbalanced load conditions. Experiments validate simulation results where the low-order voltage harmonics show that the d3-q3 voltage vector is null.
Date of Publication: July 2010