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Defects, fault coverage, yield and cost, in board manufacturing

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2 Author(s)
Tegethoff, M.M.V. ; Hewlett-Packard Co., Fort Collins, CO, USA ; Chen, T.W.

An analysis of the main contributors to the quality and cost of complex board manufacturing is presented. Manufacturing data from three boards built at Hewlett-Packard and simulation models are used to derive the sensitivity of quality and cost versus Surface Mount Technology (SMT) solder defect rate component functional defect rate and test coverage. A new yield model which accounts for the clustering of solder defects is introduced and a first order estimation of the cost of implementing the IEEE 1149.1 standard on ASICs is given

Published in:

Test Conference, 1994. Proceedings., International

Date of Conference:

2-6 Oct1994