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Three-Transistor DRAM-Based Content Addressable Memory Design for Reliability and Area Efficiency

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3 Author(s)
Wei-Ning Hsu ; Dept. of Electron. Eng., Nat. Changhua Univ. of Educ., Changhua, Taiwan ; Tsu-Hsin Wu ; Tsung-Chu Huang

Content addressable memory is widely used in communication network, inference machine and cache system. In this paper a three-transistor DRAM-based content ad-dressable memory cell design is proposed based on the Berger and m-out-of-n codes. The coding cannot only approve to reduce the redundant transistors but also provide a totally self-check for refresh and error detection mechanism for reliability. A novel Berger invert code is presented for improve the dependability for about 21% and information energy for 25%. From a variety of post-layout SPICE simulations, the search-match delay time cab be controlled under typical DRAM-based CAM level and the area efficient can be improved by almost double.

Published in:

Memory Technology, Design, and Testing, 2009. MTDT '09. IEEE International Workshop on

Date of Conference:

Aug. 31 2009-Sept. 2 2009

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