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An effective BIST scheme for ring-address type FIFOs

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3 Author(s)
Zorian, Y. ; AT&T Bell Labs., Princeton, NJ, USA ; van de Goor, A.J. ; Schanstra, I.

FIFO memories impose special test problems because of their built-in addressing restrictions and access limitations. With the increasing usage of FIFOs today, generic algorithms are needed to test stand-alone FIFO chips and embedded FIFO macros. This paper addresses the problem of testing a very popular type of FIFO, namely the ring-address FIFO. It introduces two novel algorithms to test this type of FIFO. Both algorithms provide full fault coverage for a comprehensive fault model. The first algorithm uses a generic test approach in the sense that it does not require any change to the FIFO hardware. Whereas, the second algorithm is DFT-based. It assumes access to a FIFO design and suggests minor DFT modifications, in order to reduce the test complexity from O(n2) to O(n). The BIST architecture of the DFT-based algorithm, which has recently been utilized in different products, is also described

Published in:

Test Conference, 1994. Proceedings., International

Date of Conference:

2-6 Oct1994