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In-system timing extraction and control through scan-based, test-access ports

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1 Author(s)
DeHon, A. ; Artificial Intelligence Lab., MIT, Cambridge, MA, USA

We present circuits and techniques which allow the extraction of fine-grained timing information using a simple, scan-based, test-access port such as the JTAG/IEEE 1149 standard. We go on to show how these techniques can be combined with other simple circuits for post-fabrication timing control. These techniques open up opportunities to perform timing oriented tests through TAP control. Further, they allow in-system timing adaptation which can be exploited to achieve high system performance

Published in:

Test Conference, 1994. Proceedings., International

Date of Conference:

2-6 Oct1994

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