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Multi-frequency, multi-phase scan chain

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2 Author(s)
Kee Sup Kim ; Microprocessor Products Group, Intel Corp., USA ; L. Schultz

The use multiple clocks presents an interesting problem to scan design. Traditionally, a separate scan chain has been provided for each clock, which results in longer than necessary scan operations due to unbalanced scan chain length. A set of methods that would allow mixing of memory elements clocked at different frequencies and phases in a single scan chain is presented and the proofs of the correct operation of the methods are given. If multiple scan chains are allowed, these methods make it possible to form scan chains of equivalent length for the savings in test application time and tester memory

Published in:

Test Conference, 1994. Proceedings., International

Date of Conference:

2-6 Oct1994