By Topic

Combined optimisation of thermal behaviour and electrical parasitics in Power Semiconductor components

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Stefan Forster ; Otto-von-Guericke-University Magdeburg, Universitätsplatz 2, Magdeburg, Germany ; Andreas Lindemann

Capacitive and inductive parasitics that exist in every electrically conducting structure are inseparably associated with the geometry. Especially in power electronic systems the geometry also is defined through thermal aspects. Investigation of the correlation between thermal optimisation of the electrically conduction structure and the influence of this reshape process on the formation of capacitive and inductive parasitics is the main task. The work aims on a combined optimisation process. Therefor PEEC (partial element equivalent circuit) method is employed to extract parasitics as lumped parameters for an adequately subdivided current path under view. Approaches for methodical application in design processes are studied.

Published in:

Power Electronics and Applications, 2009. EPE '09. 13th European Conference on

Date of Conference:

8-10 Sept. 2009