Combined optimisation of thermal behaviour and electrical parasitics in Power Semiconductor components

Capacitive and inductive parasitics that exist in every electrically conducting structure are inseparably associated with the geometry. Especially in power electronic systems the geometry also is defined through thermal aspects. Investigation of the correlation between thermal optimisation of the electrically conduction structure and the influence of this reshape process on the formation of capacitive and inductive parasitics is the main task. The work aims on a combined optimisation process. Therefor PEEC (partial element equivalent circuit) method is employed to extract parasitics as lumped parameters for an adequately subdivided current path under view. Approaches for methodical application in design processes are studied.