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Design and analysis of flash translation layers for multi-channel NAND flash-based storage devices

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4 Author(s)
Sang-Hoon Park ; Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea ; Seung-Hwan Ha ; Kwanhu Bang ; Eui-Young Chung

NAND flash-based storage devices (NFSDs) have been replacing the conventional magnetic storage devices in many consumer electronic systems. One of the advantages of NFSDs is their read/write bandwidth, which is higher than that of the magnetic storage devices. For further increase of their bandwidth, high-end NFSDs employ multichannel and multi-way architectures in which it is possible to access the NAND flash memories (NFMs) in parallel for amortizing the long latency of NFMs. Even though this architecture provides higher bandwidth from the hardware perspective, the overall performance of an NFSD critically depends on how efficiently the multiple channels and ways are utilized. In this regard, the key design component is an intermediate software layer called flash translation layer (FTL), since it manages the hardware resources as well as data. To the best of authorsiquest knowledge, this is the first work to propose a general method to design an FTL for multichannel / multi-way NFSDs (FTL-MM). The proposed design method consists of two steps. First, we design an FTL for a single-channel / single-way NFSD (FTL-SS). Second, we extend the FTL to support an NFSD with an arbitrary number of channels and ways. To prove the generality and effectiveness of the proposed method, we apply the method to three well-known FTLs. The experimental results indicate that the FTLs enhanced by our approach are comparable to the ideal FTL and that their performance is scalable to various channel / way architectures. Quantitatively speaking, the average channel utilization decreases by at most 10%, when we increase the number of channels and ways up to four.

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Consumer Electronics, IEEE Transactions on  (Volume:55 ,  Issue: 3 )