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A 33-dBm P 0.1-dB single-pole double-throw antenna switch is designed and implemented using a standard 0.18-mum CMOS process at 1.8 GHz. An analysis shows a relation between parasitic junction capacitors and substrate resistance for low insertion loss (IL). The power-handling capability of the switch was also investigated through the voltage dividing mechanism through the substrate in the case of an ON-insertion loss-state NMOS switch implemented in a triple-well structure. A multistacked field-effect transistor (FET) structure with feed-forward capacitors in an Rx switch was chosen as the method of designing an antenna switch with high power-handling capability. Low IL of the switch in the multistacked FET structure is achieved by the optimization of layout and minimization of junction capacitors through the deep N-well bias. Allowance of a negative voltage swing at either the source or drain port is ensured by a floated well structure with a negatively biased P-well for each switch device of the multistacked FET structure. Intentional unequal division of the voltage swing level at each NMOS device by feed-forward capacitors with negative biases of the off-state switches helps to prevent channel formation in the off-state device. Experimental data shows that the proposed design achieves a 0.1-dB compression point at 33-dBm input power at 1.8 GHz with a negative bias supply to control the voltage at the off-state switches and the P -well of each device. The IL of the Tx switch is 0.5 and 0.73 dB at 900 MHz and 1.8 GHz, respectively. The Rx switch has 0.7- and 1.1-dB IL at 900 MHz and 1.8 GHz, respectively. In addition, a reliability issue related to antenna load mismatch was tested using a load-pull measurement setup.