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In this paper we intend to present a new architecture of direct digital frequency synthesis (DDFS) which want to reduce the switching time between two different frequencies. We start from a classical DDFS which was first implemented on a FPGA device presented in paper using the Tierney architecture. In paper is presented a classical DDFS architecture and in this paper we present a new architecture which intend to extend the output frequency range, but to not reduce the switching time between two desired frequencies. To reduce the switching time we implement two DDFS devices. The frequency ranges that can be generated by these two DDFSs are selected in such a manner that can cover two distinct ranges. To reduce the switching time we implement a selection circuit that decides which DDFS circuit is proper to be activated to obtain a shorter time to produce the desired frequency signal. These two DDFSs circuits and the selection circuit are implemented in a FPGA device to be able to evaluate the functionality and performances of this type of frequency generator.