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A VLSI design for a real-time video decoder

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4 Author(s)
Chan, Y.K. ; Dept. of Comput. Sci., City Univ. of Hong Kong, Kowloon, Hong Kong ; Kwong, S. ; Chan, K.L. ; Wong, T.F.

This paper presents the design of a VLSI implementation of a real-time video decoder. The video decoder can decode a motion CIF format video sequence from a data rate of 5 kbyte/frame at 30 frames/sec with a signal-to-noise ratio of 32 dB. It is found that the real-time decoder has a better performance when compared with previous implementations. The static decompression part of the decoder is based on the SDIC algorithm. The major advantage of the SDIC algorithm is the hardware simplicity and its VLSI realization. In this paper, the hardware design of the real-time decoder and results are presented

Published in:

VLSI Signal Processing, VIII, 1995. IEEE Signal Processing Society [Workshop on]

Date of Conference:

16-18 Oct 1995

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