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Hierarchical synthesis based on pareto-optimal fronts

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3 Author(s)
E. Roca ; IMSE, CSIC and University of Sevilla Sevilla, Spain ; R. Castro-Lopez ; F. V. Fernandez

Pareto-optimal fronts have recently arisen as a promising alternative for design space exploration, potentially enabling better and more efficient hierarchical synthesis. This paper reviews the Pareto front generation problem, extends this concept to reconfigurable circuits, and discusses alternative applications to hierarchical synthesis approaches.

Published in:

Circuit Theory and Design, 2009. ECCTD 2009. European Conference on

Date of Conference:

23-27 Aug. 2009