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Power grid optimization is required to minimize the risks of timing error by IR drop, defects by electro migration (EM), and manufacturing cost by the chip size. We propose a new approach by observing the direct objectives of manufacturing cost, and timing error risk. The optimization is executed in early phase of the physical design, and the purpose is to find the rough budget of decoupling capacitors that may cause block size increase. This approach enables selection of a cost sensitive result or a performance sensitive result.