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A new high speed, low power adder; using hybrid analog-digital circuits

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2 Author(s)
Taherinejad, N. ; Electr. Eng. Dept., Iran Univ. of Sci. & Technol., Tehran, Iran ; Abrishamifar, A.

In this paper a new high speed and low power adder is presented. The circuit uses a hybrid concept of analog and digital circuit design to propagate the carry and so achieve a Full Adder with 78 ps delay and 7.26 muW of power consumption. SPICE Simulations performed on the 0.18 mum TSMC Technology demonstrates the average improvement of 159%, 184% and 516%, respectively for delay, power consumption and PDP.

Published in:

Circuit Theory and Design, 2009. ECCTD 2009. European Conference on

Date of Conference:

23-27 Aug. 2009