By Topic

A new fault attack on the advanced encryption standard hardware

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Mukhopadhyay, D. ; Dept. of Comput. Sc & Eng., Indian Inst. of Technol. Kharagpur, Kharagpur, India

The present paper develops a new fault attack suitable against hardware designs of the advanced encryption standard (AES) cryptosystem. The paper presents a two stage fault based attack of an AES implementation that assumes a random non-zero random byte fault at the input of the eighth round. The paper shows that the fault model is practical, does not assume the location of the byte fault in the state matrix and requires a brute force search of complexity 236. The paper discusses the possibility of the attack on an FPGA implementation of AES by making sudden changes in the frequency of the input clock.

Published in:

Circuit Theory and Design, 2009. ECCTD 2009. European Conference on

Date of Conference:

23-27 Aug. 2009