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The present paper develops a new fault attack suitable against hardware designs of the advanced encryption standard (AES) cryptosystem. The paper presents a two stage fault based attack of an AES implementation that assumes a random non-zero random byte fault at the input of the eighth round. The paper shows that the fault model is practical, does not assume the location of the byte fault in the state matrix and requires a brute force search of complexity 236. The paper discusses the possibility of the attack on an FPGA implementation of AES by making sudden changes in the frequency of the input clock.