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A low-power, 32-bit RISC processor with signal processing capability and its multiply-adder

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3 Author(s)
Nadehara, K. ; Inf. Technol. Res. Lab., NEC Corp., Kawasaki, Japan ; Hayashida, M. ; Kuroda, I.

A 500 mW, 100 MHz, 32-bit RISC microprocessor, designed for software signal processing is described. Its signal processing oriented instruction set includes fast integer/fixed-point multiply/multiply-accumulate instructions, minimum/maximum instructions and conditional branch instructions with prediction etc. The processor integrates a 200 MHz, 32-bit compact multiply-adder with a parallel overflow detector in its pipeline to achieve peak signal processing performance of 200 MOPS. Through the employment of this fast multiply-adder, this microprocessor is able to obtain higher signal processing performance than other RISC processors

Published in:
VLSI Signal Processing, VIII, 1995. IEEE Signal Processing Society [Workshop on]

Date of Conference: 16-18 Oct 1995

Page(s):
51 - 60
Meeting Date :
16 Sep 1995-18 Sep 1995
Print ISBN:
0-7803-2612-1
INSPEC Accession Number:
5225193
Conference Location :
Sakai
Digital Object Identifier :
10.1109/VLSISP.1995.527476
Product Type:
Conference Publications

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