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A somewhat novel approach is presented for determining FSM state codes. Instead of producing an assignment designed to minimise the overall logic of the machine, all Moore outputs are converted to state bits. Pure state bits are only introduced as a final resort. This results in very simple output equations at the expense of more complex next state equations. The total number of output and state bits is usually reduced-a feature that has major advantages on most PLDs. Perhaps the greatest advantage, though, is that outputs are glitch-free. The propagation delays for PLD implementations are also minimised.