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Verification of a production cell controller using symbolic timing diagrams

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2 Author(s)
R. Schlor ; OFFIS, Oldenburg, Germany ; F. Korf

This paper presents three novel aspects of system-level hardware design: a graphical specification language called STD (symbolic timing diagrams), a design methodology with formal verification of each development step, and a powerful automatic verification tool, which owes its efficiency to sophisticated optimization techniques exploiting the properties of the specification language STD. The techniques are fully implemented in ICOS (interface controller synthesis and verification system). We present a “real-life” case-study to demonstrate the feasibility of the approach

Published in:

Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European

Date of Conference:

18-22 Sep 1995