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Design and use of a system-level specification and verification methodology

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2 Author(s)
Hashmi, M.M.K. ; Design Autom. Centre, ICL, Manchester, UK ; Bruce, A.C.

This paper describes the problem of Design Capture at System level and of moving a design verifiably down levels of abstraction. We describe our steps on the way to designing a methodology which captures system level interface and functional specifications, and enables the designers to decompose and refine specifications down to RTL VHDL in a hierarchic and piece-wise manner

Published in:

Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European

Date of Conference:

18-22 Sep 1995