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Hardware-software co-synthesis of fault-tolerant real-time distributed embedded systems

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2 Author(s)
Srinivasan, S. ; Dept. of Electr. Eng., Princeton Univ., NJ, USA ; Jha, N.K.

Distributed systems are becoming a popular way of implementing many embedded computing applications, automotive control being a common and important example. Such embedded systems typically have soft or hard performance constraints. The increasing complexity of these systems makes them vulnerable to failures and their use in many safety-critical applications makes fault tolerance an important requirement. This peeper is the first to address the problem of automatic hardware-software co-synthesis of fault-tolerant embedded distributed real-time systems in a generalized scenario. We present an algorithm which tales as input the specification of the data-flow information in the form of a task graph, the performance constraints, the fault tolerance requirements and the available hardware resources in the form of processor, ASIC and link libraries. Our algorithm then synthesizes the required hardware as a distributed system in terms of the component processors, ASICs and interconnection links. The tasks are mapped to this hardware such that the overall system cost is minimized while still meeting the performance constraints and the fault tolerance requirements. Our algorithm uses clustering techniques to perform the synthesis. Fault tolerance is added using CRAFT, a technique we recently proposed for CRiticAlity based Fault Tolerance in real-time distributed systems

Published in:

Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European

Date of Conference:

18-22 Sep 1995

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