By Topic

An adaptive distributed algorithm for sequential circuit test generation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
J. Sienicki ; Dept. of Electr. & Comput. Eng., Rutgers Univ., Piscataway, NJ, USA ; M. Bushnell ; P. Agrawal ; V. Agrawal

We describe the parallelization of sequential circuit test generation on an Ethernet-connected network of SUN workstations. We use the observations of the previous work to execute the program in two phased. All processors simultaneously ran the test generation program, Gentest. In the first phase, the fault list is equally divided among processors, each of which derives tests for targets from its list. A time limit is used to abandon the search for a test for hard to detect faults. Any test found is immediately used to simulate all faults, including those assigned to other processors. Due to the sequential nature of the circuit test vectors are not shared, but the fault simulation data are shared among processors. This phase terminates when only hard to detect faults are left. In the second phase, each remaining fault is simultaneously targeted by all processors, which now have different initial states of the circuit. The first processor to find the test interrupts all others, at which point all processors simultaneously target the next remaining fault. The results show that with this dual strategy, the speedup can be made to increase almost linearly, or sometimes superlinearly, with the number of processors

Published in:

Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European

Date of Conference:

18-22 Sep 1995