Referenced Items are not available for this document.
We examine delay model used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which significantly affect the actual delays, but which are not taken into account by the existing model used in testing. Our analysis questions the test quality offered by test generation procedures used so far
Published in:
Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European
Date of Conference: 18-22 Sep 1995
- Page(s):
- 196 - 201
- Meeting Date :
- 18 Sep 1995-22 Sep 1995
- Print ISBN:
- 0-8186-7156-4
- INSPEC Accession Number:
- 5100246
- Conference Location :
- Brighton
- Digital Object Identifier :
- 10.1109/EURDAC.1995.527408
- Product Type:
- Conference Publications
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