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Quality considerations in delay fault testing

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2 Author(s)
Pierzynska, A. ; Sch. of Comput. Sci., Simon Fraser Univ., Burnaby, BC, Canada ; Pilarski, S.

We examine delay model used in VLSI circuit testing. Our study includes electrical-level simulation experiments with HSPICE. We show phenomena which significantly affect the actual delays, but which are not taken into account by the existing model used in testing. Our analysis questions the test quality offered by test generation procedures used so far

Published in:

Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European

Date of Conference:

18-22 Sep 1995