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A hardware/software partitioning algorithm for pipelined instruction set processor

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4 Author(s)
Binh, N.N. ; Dept. of Inf. & Comput. Sci., Toyohashi Univ. of Technol., Japan ; Imai, M. ; Shiomi, A. ; Hikichi, N.

This paper proposes a new method to design an optimal instruction set for pipelined ASIP development using a formal HW/SW codesign methodology. The codesign task addressed in this paper is to find a set of HW implemented operations to achieve the highest performance of a pipelined ASIP under a given gate count and power consumption constraint. The method enables to estimate the performance and pipeline hazards of the designed ASIP very accurately. The experimental results show that the proposed method is effective and quite efficient

Published in:

Design Automation Conference, 1995, with EURO-VHDL, Proceedings EURO-DAC '95., European

Date of Conference:

18-22 Sep 1995

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