By Topic

The signal delay in interconnection lines considering the effects of small-geometry CMOS inverters

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
M. -C. Shiau ; Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; C. -Y. Wu

Physical timing models for small-geometry CMOS inverters with interconnection lines have been developed. Large-signal equivalent circuits of CMOS inverters and 10-section RC ladder networks for interconnection lines are considered assuming nonstep input waveforms and initial delay times. Due to more realistic and complete considerations, the model accuracy is expected to be higher than that of the conventional delay models. Extensive comparisons between model calculations and SPICE simulations show that the models have a maximum relative error of 16% on the delay times of CMOS inverters with interconnection lines of different R and C values and section numbers N and different gate sizes, device parameters, and even input excitation waveforms. Reasonable accuracy, wide applicable range, and high computational efficiency make the timing models quite attractive in MOS VLSI timing verification and autosizing

Published in:

IEEE Transactions on Circuits and Systems  (Volume:37 ,  Issue: 3 )