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3D integration process flow for set-top box application: Description of technology and electrical results

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12 Author(s)
S. Cheramy ; CEA Léti - MINATEC; 17 rue des Martyrs; F-38054 GRENOBLE - France ; J. Charbonnier ; D. Henry ; A. Astier
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In this paper, the technological steps specifically developed for 3D integration of a set top box demonstrator will be presented (figure 1). The integration flow is based on a 45nm node technology top chip stacked on a 130nm node technology active bottom wafer. This flow needed to develop specific wafer level packaging technologies such as: Top & bottom chips interconnections; Temporary bonding and debonding of bottom wafer; High aspect ratio TSV's designed into the bottom wafer; Backside interconnections for subsequent packaging step; Top chip stacking on bottom wafer In this paper, the complete process flow will be presented. Then, a technical focus will be done on the most important process steps for the 3D integration. The preliminary electrical results of the demonstrator will be discussed. Finally, some prospects for 3D integration technologies and applications will be proposed.

Published in:

Microelectronics and Packaging Conference, 2009. EMPC 2009. European

Date of Conference:

15-18 June 2009