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A study of thermal performance for chip-in-substrate package on package

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4 Author(s)
Tuan-Yu Hung ; Dept. of Power Mech. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Ming-Chih Yew ; Chan-Yen Chou ; Kuo-Ning Chiang

The three-dimensional package (3D package) is one of the popular designs for high-density packages. The chip-in-substrate (CiS)-type structure is one of the popular manners in 3D package because of the resulting improvement in package-stacking ability. To study its thermal performance, the finite element (FE) analysis is applied in this study. The designed dummy solder bumps and relatively better power arrangement conditions are proposed to improve the thermal performance of the package. The dummy solder bumps under the chip can improve the efficiency of heat dissipation from the chip to the printed circuit board (PCB). Moreover, the highest power dissipation is suggested to be placed at the lower chip. Thus, the thermal performance of the CiS packaging technology can be further enhanced, and it is suitable for applications on high-power IC devices.

Published in:

Microelectronics and Packaging Conference, 2009. EMPC 2009. European

Date of Conference:

15-18 June 2009