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This paper will summarize joint work between ST Microelectronics, Amkor Technology and Nokia; to qualify Amkor's through mold via (TMVtrade) bottom package technology for next generation high density PoP applications. The 12 times 12 mm daisy chain test vehicle reported in this joint work includes a thin flip chip die in a fully molded bottom package with 516 bottom BGAs at 0.4 mm pitch and 168 top solderable through mold vias at 0.5 mm pitch. This paper will report the package level (moisture resistance, temperature cycling) and board level (temperature cycle, drop) qualification data against IC and handheld application requirements. Additional data for package warpage control and board level reliability for larger PoP applications using TMV technology will be included beyond what was reported at ECTC, SMTA International during 2008 and IMAPS Device Packaging in March 2009, based on a 14 times 14 mm daisy chain test vehicle with 620 bottom BGAs at 0.4 mm pitch and 200 top vias at 0.5 mm pitch. Additional data on the TMV technology will be provided including: maximum die to package size design benefits for wirebond, stacked and flip chip die, coplanarity and package warpage measured by shadow moireacute across lead free SMT reflow profiles. JEDEC standardization work for next generation PoP applications will be provided for mechanical and high density electrical interface requirements driven by low power double data rate 2 memory (LP DDR2), in single and dual channel architectures which require 0.5 and 0.4 mm pitch interfaces respectively.