By Topic

Next generation leadless RF packages utilizing 1st level low cost flip chip interconnect technology

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Walczyk, S. ; IS&O, CSC-Innovation, NXP Semicond. Netherlands B.V., Nijmegen, Netherlands ; Dijkstra, P. ; Kramer, N. ; Verspeek, J.

There is an ongoing demand for low cost high performance RF components for high frequency applications. Current packages for this domain use plastic packages based on wirebonding. The RF performance is limited by parasitic effects due to the RLC network between the wirebond from the dies to the leadframe. One of the best ways to reduce these effects is the use of flip chip technology. Flip chip interconnections are essential as they provide minimal emitter inductance. Thus the device speed and signal integrity with the lower inductance interconnection makes flip chip most expedient for RF devices. A low cost leadless packaging concept using flip chip interconnects will be presented. The package technology chosen is called UTLP (ultra thin leadless package). This technology is based on a leadframe, consisting of a three layer metal stack. The aluminum bond pads of the dies are plated with an electroless nickel immersion gold (ENIG) under bump metallization. The flip chip Pb-free solder bumps (SnAgCu) are created by means of a stencil printing process on the die rather than using expensive lithography as the 1st level interconnects. The fine bump pitches of 200 mum on the discrete dies offer not only cost advantages but also allow for further miniaturization. The challenges with the interaction of the resulting limited solder volume and the leadframe finish are illustrated. Solutions to circumvent the possible existence of brittle AuSn4 intermetallic formations at this interface are described. The assembly flow and life testing results are presented.

Published in:

Microelectronics and Packaging Conference, 2009. EMPC 2009. European

Date of Conference:

15-18 June 2009