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This paper dealt with the following topics: MR heads; RFIC and novel protection devices; system level and other ESD issues; on-chip protection strategies, physics, and modeling; devices effects tester; ESD design failures analysis and modeling; factory and materials; on-chip protection characterization; novel LTP testers; and, magnetic recording heads.

Published in:

Electrical Overstress/Electrostatic Discharge Symposium, 2004. EOS/ESD '04.

Date of Conference:

19-23 Sept. 2004