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The effect of high pin-count ESD tester parasitics on transiently triggered ESD clamps

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5 Author(s)
Hans Kunz ; Texas Instruments Inc, 12500 TI Boulevard, Dallas, TX 75243 USA ; Robert Steinhoff ; Charvaka Duvvury ; Gianluca Boselli
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Conflicting HBM ESD results are presented for several ESD testers/test-configurations, all of which pass the present tester specifications. The discrepancy is attributed to parasitic capacitance, which can deactivate the dV/dt-detection of an ESD circuit. An unexpectedly large (>1 nF) effective parallel capacitance is found by summing tester relay capacitances of unstressed pins, connected through on-chip current paths, while considering the Miller effect. An ESD strike between two pins and the symmetric "reverse-pin, reverse-polarity" strike are shown to be nonequivalent due to a different set of on-chip current paths.

Published in:

Electrical Overstress/Electrostatic Discharge Symposium, 2004. EOS/ESD '04.

Date of Conference:

19-23 Sept. 2004