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Design on latchup-free power-rail ESD clamp circuit in high-voltage CMOS ICs

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2 Author(s)
Kun-Hsien Lin ; Nanoelectron. & Gigascale Syst. Lab., Nat. Chiao-Tung Univ., Hsinchu, Taiwan ; Ming-Dou Ker

The holding voltage of the high-voltage ESD protection devices in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristics will cause the high-voltage CMOS ICs susceptible to the latchup-like danger in the real system applications, especially while these devices are used in the power-rail ESD clamp circuit. A new latchup-free design on the power-rail ESD clamp circuit with stacked-field-oxide structure is proposed and successfully verified in a 0.25-mum 40-V CMOS process to achieve the desired ESD level. The total holding voltage of the stacked-field-oxide structure in snapback breakdown condition can be larger than the power supply voltage. Therefore, latchup or latchup-like issues can be avoided by stacked-field-oxide structures for the IC applications with VDD of 40 V.

Published in:

Electrical Overstress/Electrostatic Discharge Symposium, 2004. EOS/ESD '04.

Date of Conference:

19-23 Sept. 2004

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