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Noise impact of single-event upsets on an FPGA-based digital filter

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5 Author(s)
Brian H. Pratt ; NSF Center for High Performance, Reconfigurable Computing (CHREC), Dept. of Elec. & Comp. Engineering, Brigham Young University, Provo, UT 84604 USA ; Michael J. Wirthlin ; Michael Caffrey ; Paul Graham
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Field-programmable gate arrays are well-suited to DSP and digital communications applications. SRAM-based FPGAs, however, are susceptible to radiation-induced single-event upsets (SEUs) when deployed in space environments. These effects are often handled with the area and power-intensive TMR mitigation technique. This paper evaluates the effects of SEUs in the FPGA configuration memory as noise in a digital filter, showing that many SEUs in a digital communications system cause effects that could be considered noise rather than circuit failure. Since DSP and digital communications applications are designed to withstand certain types of noise, SEU mitigation techniques that are less costly than TMR may be applicable. This could result in large savings in area and power when implementing a reliable system. Our experiments show that, of the SEUs that affected the digital filter with a 20 dB SNR input signal, less than 14% caused an SNR loss of more than 1 dB at the output.

Published in:

2009 International Conference on Field Programmable Logic and Applications

Date of Conference:

Aug. 31 2009-Sept. 2 2009