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Multibit Error-Correction Methods for Latency-Constrained Flash Memory Systems

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3 Author(s)
Priyanka P. Ankolekar ; Spansion Inc. , Sunnyvale, CA, USA ; Roger Isaac ; Jonathan W. Bredow

This paper presents multibit error-correction schemes for nor Flash used specifically for execute-in-place applications. As architectures advance to accommodate more bits/cell and geometries decrease to structures that are smaller than 32 nm, single-bit error-correction codes (ECCs) are unable to compensate for the increasing array bit error rates, making it imperative to use 2-b ECC. However, 2-b ECC algorithms are complex and add a timing overhead on the memory read access time. This paper proposes low-latency multibit ECC schemes. Starting with the binary Bose-Chaudhuri-Hocquenghem (BCH) codes, an optimized scheme is introduced which combines a multibit error-correcting BCH code with Hamming codes in a hierarchical manner to give an average latency as low as that of the single-bit correcting Hamming decoder. A Hamming algorithm with 2-b error-correcting capacity for very small block sizes (< 1 B) is another low-latency multibit ECC algorithm that is discussed. The viability of these methods and algorithms with respect to latency and die area is proved vis-a??-vis software and hardware implementations.

Published in:

IEEE Transactions on Device and Materials Reliability  (Volume:10 ,  Issue: 1 )