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Motion estimation (ME) is the most computationally intensive and the most power consuming part of video compression and video enhancement systems. In this paper, we propose a novel power reduction technique for ME hardware. We quantified the impact of glitch reduction, clock gating and the proposed technique on the power consumption of two full search ME hardware implementations on a Xilinx Virtex II FPGA using Xilinx XPower tool. Glitch reduction and clock gating together achieved an average of 21% dynamic power reduction. The proposed technique achieved an average of 23% dynamic power reduction with an average of 0.4 db PSNR loss. The proposed technique achieves better power reduction than pixel truncation technique with a similar PSNR loss.