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Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors

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4 Author(s)
Sano, T. ; Dept. of Inf. & Comput. Sci., Keio Univ., Yokohama, Japan ; Saito, Y. ; Kato, M. ; Amano, H.

Based on the power consumption analysis of a real dynamically reconfigurable processor array (DRPA) prototype MuCCRA-3, it appears that the key of power saving is keeping the datapath on the processing element (PE) array as possible. Fine grain partial reconfiguration (FGPR) is a simple technique to minimize the change of configuration code in a hardware context switching. In FGPR, a configuration code is divided into several components and only the configuration data for the required components are changed. Evaluation results demonstrate that about 15% of the power consumption is reduced with only 0.7% hardware overhead. The total amount of configuration data and its loading time can be also reduced by 37% in average.

Published in:

Field Programmable Logic and Applications, 2009. FPL 2009. International Conference on

Date of Conference:

Aug. 31 2009-Sept. 2 2009

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