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New multi threshold voltage (multi-Vth) brute-force FinFET sequential circuits with independent-gate bias, work-function engineering, and gate-drain/source overlap engineering techniques are presented in this paper. The total active mode power consumption, the clock power, and the average leakage power of the multi-Vth sequential circuits are reduced by up to 55%, 29%, and 53%, respectively, while maintaining similar speed and data stability as compared to the circuits in a single threshold voltage (single-Vth) tied-32 nm-gate FinFET technology. Furthermore, the area is reduced by up to 21% with the new sequential circuits as compared to the circuits with single-Vth tied-gate FinFETs.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:19 , Issue: 1 )
Date of Publication: Jan. 2011