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Fixed-State Tests for Delay Faults in Scan Designs

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2 Author(s)
Irith Pomeranz ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Sudhakar M. Reddy

One of the methods to reduce the power dissipation during scan shifting is based on holding the state inputs to the combinational logic of a circuit constant for the duration of a scan operation. We note that this method also allows a new type of two-pattern scan-based tests to be applied. We refer to these tests as fixed-state tests. These tests have several properties that make them effective as complements to skewed-load and broadside tests, and also allows them to be computed efficiently. We discuss these properties in the context of transition faults. We describe procedures for selecting the constant vector for the state inputs during a scan operation, and for generating fixed-state tests. We present experimental results to demonstrate the transition fault coverage improvements possible with these tests.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:19 ,  Issue: 1 )