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Multiprocessor System-on-Chip is a promising realization alternative for the next generation of computing architectures providing the required data processing performance in high performance computing applications. Numerous scientists from industry and academic institutions investigate and develop novel processing elements and accelerators as can be seen in real devices like IBM's Cell or nVIDIA's Tesla GPU. Nevertheless, the on-chip communication of these multiple processor elements has to be optimized tailored to the actual requirement of the data to be processed. Network-on-Chip (NoC), Bus-based or even heterogeneous communication on chip often suffer from the fact of being inflexible due to their fixed physical realization. This paper presents a novel approach for a NoC, exploiting circuit-and packed-switched communication as well as a run-time adaptive and heterogeneous topology. An application scenario from image processing exploiting the implemented NoC on an FPGA delivers results like performance data and hardware costs.