Investigation of a Sequential Three-Dimensional Process for Back-Illuminated CMOS Image Sensors With Miniaturized Pixels

A new 3-D CMOS image sensor architecture is presented as a potential candidate for submicrometer pixels. To overcome the scaling challenge related to miniaturized pixel design rules, far beyond traditional 3-D stacking alignment capabilities, a sequential construction is applied. This paper gives a technical overview of this 3-D scheme and validates a part of its building blocks. As a consequence of a sequential process, the thermal budget is limited to ensure bottom device immunity. Subsequently, high-quality SOI film transfer above the first layer by direct bonding and etch back is demonstrated. Finally, the low-temperature processing of HfO
₂
/TiN fully depleted silicon-on-insulator readout transistors is detailed and evaluated from a low frequency noise point of view.