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Physics and design optimization of ESD diode for 0.13μm PD-SOI technology

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5 Author(s)
Christophe Entringer ; ST Microelectronics Crolles, 850,rue Jean Monnet F-38926 Crolles Cedex ; Philippe Flatresse ; Pascal Salome ; Pascal Nouet
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This paper investigates the physics of 0.13 mum partially depleted SOI gated diodes through TLP measurements and TCAD simulations. The impact of gate length, well type, oxide thickness, gate to contact distance and presence of gate on ESD performance are evaluated and discussed. It is shown that the gate coupling effect decreases ESD performance.

Published in:

Electrical Overstress/Electrostatic Discharge Symposium, 2005. EOS/ESD '05.

Date of Conference:

8-16 Sept. 2005