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Manycore systems are expected to emerge as the dominant trend in next generation computer systems. These parallel systems are expected to be interconnected via packet-based Networks-on-Chip (NoC). As such, they present several educational challenges, as their design is affected by a large number of NoC-based design-space parameters. NoC-based manycore systems demand modifications in the existing computer related teaching curricula. In this work we present a practical FPGA-based teaching framework to emulate NoC-based manycore systems that instructors can utilize to teach students the fundamental design concepts of NoC-based manycore systems and their integration through a series of VHDL laboratory assignments.