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This paper focused on the process of forming sidewall insulation of through silicon via (TSV) which was a challenging bottleneck in 3D integration technologies. In traditional way, etching silicon oxide on via bottom would reduce the thickness of sidewall insulation layer inevitably, which might lead to the failure of TSV sidewall insulation and electrical interconnection characteristic. In this paper, the parylene-C (called parylene herein) film was used to cover the silicon oxide of via in the anisotropic etching process, which prevented the silicon oxide at the sidewall from being etched. Using this method, a well sidewall insulation layer was fabricated successfully. The sidewall thickness of oxide layer gained 0.93 mum, 0.49 mum, and 0.40 mum at the top part, middle part of the via and the via-base respectively after etching process.