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High end networking and computing applications continue to drive silicon technologies for higher data rates and increased bandwidth. The push for silicon performance also drives a need for packaging performance to deliver clean and efficient power to the device. This paper compares the electrical performance of three new advanced packaging technologies designed to improve the DC and AC power delivery network in a network ASIC (Application Specific Integrated Circuit). A baseline component in conventional buildup with top-side capacitors was redesigned into three advanced package configurations: (1) a package utilizing a conventional buildup substrate, but with capacitors moved to the bottom ball-side of the package, (2) a package using a coreless substrate, and (3) a package using a coreless substrate, and with bottom ball-side capacitors. The package design, signal routing, device, and system and test environments are essentially unchanged, so the differences are attributed primarily to the substrate and package technology itself. Substrate, package, and system level electrical performance tests were performed and compared with the production baseline component design.