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In the case of embedded chip type CSPs (Chip Scale Packages) made by embedding chips in PCBs (Printed Circuit Boards), problems occur due to differences in the CTE (Coefficient of Thermal Expansion) between the PCBs and the chips. This study tested a method to solve this problem by inserting thermal SBLs (Stress Absorbing Layers) into the embedded chips, thereby improving the reliability of the connection between the chip and the PCB. This study focused on a production method used to form a SBL on a Silicon Active Layer in order to make embedded PCBs and the material used as SBLs was absorbent in the polyimide family, which was composed of a material containing at least 30% polysiloxanes. For the experiment, two types of samples were used, including: 20 mm times 20 mm sized silicon active layers without any SBL formed on them; those with an SBL formed only on the top surface. The samples were produced and placed on the PCBs. To examine the effects of the physical damage, 3 point bending tests were conducted and the results were analyzed.