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Test scheme of SOC test with multi-constrained to reduce test time

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3 Author(s)
Chuanpei Xu ; Sch. of Electron. Eng., Guilin Univ. of Electron. Technol., Guilin, China ; Jing Zhang ; Min Zhang

SOC integrates an intact system on one single chip, so that the size of chip is dwindled. However, the difficulty and complexity of system circuit testing is increased. Kinds of constraint conditions should be considered in testing cores, in order to meet the high-performance requirements of circuit system test, including the realization of parallel module test with test power and priority constrains. SOC test structural optimization is NP-hard problem, and it is hard to be solved using the common traditional arithmetic because of its complexity. While quantum search algorithm may reach to N magnitude acceleration, it is applicable to solve NP problems. In this paper, by combining quantum algorithm with encapsulation standards based on test bus and IEEE P1500 test wrapper, the policy of TAM based on test bus is analyzed. Firstly a mathematical model of SOC test scheme with test power and priority constraints is presented based on the quantum algorithm, by distributing TAM width, choosing an appropriate parameter, and using the superiority of quantum bit in solving NP problems. Next correlative test scheme algorithm is designed. Then, in the paper partial SOC circuits in ITC'02 test benchmarks are taken as experimentation objects. Compared with other similar algorithms, experimental results showed that QA has a better performance and it gets a comparatively shorter testing time.

Published in:

Electronic Packaging Technology & High Density Packaging, 2009. ICEPT-HDP '09. International Conference on

Date of Conference:

10-13 Aug. 2009