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This paper presents a circuit level soft error-tolerant-technique, called RRC (robust register caching), for the register file of embedded processors. The basic idea behind the RRC is to effectively cache the most vulnerable registers in a small highly robust register cache built by circuit level SEU and SET protected memory cells. To decide which cache entry should be replaced, the average number of read operations during a register ACE time is used as a criterion to judge. In fact, the victim cache entry is one which has the maximum read count. To minimize the power overhead of the RRC, the clock gating technique is efficiently exploited for the main register file resulting in significantly low power consumption. The RRC is able to protect the register file not only against single bit upsets (SBUs) but also against multiple bit upsets (MBUs) and single event transients (SETs). The RRC is experimentally evaluated using the LEON processor. The experimental results show that, if the cache size is selected properly, the architectural vulnerability factor (AVF) of the register file becomes about 1% while it imposes low power, area and performance overheads to the processor.
Date of Conference: June 29 2009-July 2 2009