A new evolutionary hardware system using FPGAS

This paper presents an implementation of evolutionary algorithm using a field programmable gate array. This novel implementation uses a high level language to hardware compilation system, called Handel-C, to produce a field programmable logic array capable of performing all the functions required of the evolutionary algorithm. EAFPGA uses Xilinx's Jbits
^TM
interface to control the generation of bit stream configuration data and the XHWIF portable hardware interface to communicate with a variety of commercially available FPGA-based hardware. EAFPGA, JBits, and XHWIF are currently being ported to the Xilinx Virtex
^TM
family of devices, which will provide greatly, increased reconfiguration speed and circuit density.