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Design for a multi-input binary adder

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1 Author(s)

The need often arises in digital systems for a fast multi-input adder capable of adding together n distinct serial binary numbers. The normal design method is to employ a parallel-series configuration of 2-input synchronous adders. It is shown how the overall speed of a multi-input adder may be enhanced using a 3-input adder stage. A circuit is described using cascaded 2- and 3-input synchronous adders, which may be clocked at 100 ns allowing the addition of six 10-bit binary numbers in lµs.

Published in:

Radio and Electronic Engineer  (Volume:39 ,  Issue: 2 )

Date of Publication:

February 1970

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