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A digitally-set potentiometer (d.s.p.) is required for any hybrid computing arrangement where iterative routines are used to establish the solution to dynamic systems. If computing accuracies of 0.1% at signal frequencies of 10 kHz are to be obtained special techniques in the design of a d.s.p. are necessary. A complete design for a 10-bit d.s.p. to fit this specification is presented, based on the use of a ladder network of low propagation delay. This in turn requires careful design of bipolar switches and a new form of switch is presented which uses f.e.t.s in the feed-back loop of monolithic d.c. amplifiers. The overall behaviour of the d.s.p. is illustrated and an estimation of errors made.